Analog & Mixed‑Signal IP built for speed, integrity, and silicon success.
We design, validate, and support high‑performance interfaces — Ethernet, USB, PCIe, SATA, MIPI, DDR, HDMI and PLLs — with an unwavering focus on signal integrity, power, and time‑to‑market.
Interface IP
Protocol‑proven PHYs, PLLs, and support collateral to accelerate bring‑up.
Silicon Support
From pre‑silicon modeling to lab validation & characterization.
Custom AMS
Tailored analog blocks for performance, area, and power budgets.
Ostiki
Lightweight knowledge base for integration guides and FAQs.
About Ostinato
We are a Silicon Valley team specializing in high‑speed AMS IP. Our ethos is in the name: Ostinato — a precise motif repeated with excellence from spec to tapeout.
What we deliver
- Production‑ready IP (PHY/PLL/clocking)
- Integration guides & models (IBIS‑AMI/Verilog‑A)
- Bring‑up checklists & compliance support
How we work
- Specification → Architecture → Silicon
- Transparent milestones & risk tracking
- Direct engineer‑to‑engineer support
Where we help
- Consumer, Automotive, Datacenter
- Advanced nodes & mature processes
- Mixed‑signal SoC integration
IP Catalog
Core protocols and building blocks. Details available on request under NDA.
Ethernet
10G/25G/40G/100G SerDes, KR/CR backplane, PAM4 options.
USB
HS/SS/SSP PHY options with robust ESD and low‑jitter clocking.
PCI Express
Gen3/Gen4‑ready SerDes with adaptive EQ and CTLE/DFE.
SATA
Low‑power SATA PHY with SSC‑friendly PLL and spread‑spectrum.
MIPI/SLVS-EC
CSI‑2/DSI D-PHY/C-PHY lanes, LVDS transceivers, SLVS-EC lanes.
DDR
PHY/Rx‑Tx slices, write leveling, Vref training, and DQS gating.
HDMI
TX PHY with pre‑emphasis and jitter‑tolerant CDR.
PLLs
Fractional‑N/Integer‑N, low‑jitter LC/RC VCOs, fast lock.
Design Services
Flexible engagements — from turnkey IP delivery to targeted consulting.
Custom Analog Blocks
PLLs, LDOs, bandgaps, ADC/DACs, DLLs and high‑speed TX/RX slices.
Spec & Architecture
Feasibility, models, performance budgets.
Design & Verification
Corner/Monte‑Carlo, AMS co‑sim, SI/PI checks.
Silicon & Bring‑up
Bench plans, ATE hooks, compliance.
Signal Integrity
Channel analysis, equalization strategy, IBIS‑AMI modeling.
- Tx/Rx optimization for target BER
- Jitter budgeting & SSC coexistence
- Compliance margining methodology
Consulting & Reviews
Architecture reviews, design audits, root‑cause analysis, training.
- AMS design reviews & mentoring
- Integration & lab debug support
- Bring‑up playbooks and checklists
Ostiki
A lightweight knowledge base for integration notes, tuning guides, and FAQs.
Getting Started
Environment setup, pin muxing, checklists.
Bring‑up Guides
Scope shots, eye diagrams, compliance tips.
FAQs
Common issues and quick fixes compiled by our support team.
Contact
San Jose, CA • support@oamsd.com